The enormous costs to manufacture microelectronical circuits require extensive simulations during design cycles in order to detect errors as early as possible, to calculate parasitic effects of small device components and to adjust the design accordingly. Simulation programs, such as SPICE, allow for the simulation of circuits with thousands of transistors on the electrical level. However, the simulation program requires compact model equations to describe individual components. This allows for realistic calculations of terminal currents and voltages. These so-called compact models represent the central, numerically efficient description of the electrical performance of individual components. Without them, the simulation of complex integrated systems would remain impossible.

At the beginning of the development of a compact model is the comprehensive analysis of the physical performance of individual component structures. This is done with the help of numerical simulations via the finite element method. Based on this, the effects which are dominated by the electrical component performance are identified. By simplifying the physics equations, a compact package equation is developed. Collaboration with technology centers provide measurement data as reference to nanostructured transistors, which are manufactured there in experiments. An implementation via the Verilog-A hardware description language allows for the integration of model packages into standard tools for network simulation.

The Nanoelectronics/ Component Modeling working group is concerned with the development of compact models to describe novel nanoelectronic devices, anticipating future generations of technology. Priorities are for instance the modeling of multiple-gate and junctionless transistor structures or tunnel field-effect transistors. Furthermore, the organic electronics laboratory is integrated in the working group, extending the research activities by the modeling of organic thin film transistors (OTFT).